1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a dynamic random access memory (DRAM) with a data latch, having a data latch circuit provided in a next stage of a sense amplifier sensing readout data from a memory cell, for transferring data at a high speed between the data latch circuit and a data bus.
2. Description of the Related Art
In accordance with the development of the technology of integrated circuits, semiconductor memory devices, particularly, DRAMs have been widely used in the field of electronics. Since the capacity of DRAM has been enlarged, the use, which requires a large amount of storage capacity as in an image memory, has been developed. However, in this field, it is required that stored data be continuously read at a high speed. When reading out memory data, the most important factor for determining the readout time is time for readout of data from a memory cell to a sense amplifier. There has been made various kinds of contrivances to apparently eliminate such readout time. For example, there is provided a DRAM with a data latch having a latch circuit connected between a sense amplifier and an I/O buffer, wherein a readout data is temporarily held.
FIG. 1 shows a main part of the general structure of a DRAM with a data latch. The DRAM with a data latch comprises a data latch circuit provided in a next stage of the sense amplifier in a memory core section of the widely used standard DRAM. In other words, The DRAM with a data latch comprises a DRAM cell array 10, a row address buffer 11, a row decoder 12, a word line level generator 13, a sense amplifier 14, a transfer gate 15, a data latch circuit 16, a column address buffer 17, a column decoder 18, a column selection gate 19, a data bus DQ, /DQ, an I/O buffer 20, a transfer gate buffer 22, and a row controller 23.
In this case, if the DRAM cell array 10 is structured of m rows and n columns, in the data latch circuit 16, n data latch circuits, which can hold data for one row, are arranged. The above structure is similar to a cache section of Cache DRAM, which has data latch circuits of n columns per one row.
FIG. 2 shows one example showing a circuit corresponding to one column of the DRAM cell array of FIG. 1, a data bus (DQ, /DQ), and a data bus load circuit 21. In FIG. 2, a dynamic memory cell MC has a capacitor C for data storage, and a MOS transistor Q for a charge transfer gate. A word line WL is connected to the memory cells MC of the same row of the memory cell array 10. (BL, /BL) denote a pair of bit lines, (DL, /DL): a data line, (DQ, /DQ): a data bus, LW: a transfer gate control signal, CSL: a column selection control signal, and /LDE: a load control signal.
The following will explain a readout operation, which is conventionally performed in the above-structured DRAM, with reference to FIGS. 1, 2 and a timing waveform of FIG. 3.
At the readout time, a /RAS (row address strobe) signal is activated, and a row address signal is inputted in synchronization with the row address strobe signal. By the activation of the /RAS signal, the row controller 23 is driven. Moreover, a word line boosted voltage, which is normally about 1.5 times higher than a power supply voltage Vcc, is generated by the word line level generator 13. The word line boosted voltage is provided as a power source of the row decoder 12, and the boosted voltage is supplied to the word line WL selected by the row decoder 12.
As mentioned above, if the word line WL is activated, data are readout to the corresponding bit lines BL or /BL from the DRAM cells corresponding to the word line. Moreover, sense amplifier control signals /SAN and SAP, which are generated by the row controller 23. Then, data of n columns on the same row read out to the bit lines BL, /BL are sensed by n number of sense amplifiers 14, and latched therein. Thereafter, the transfer gate control signal LS is activated, so that the transfer gates 15 between the sense amplifiers 14 and the data latch circuits 16 are turned on, and data latched by the sense amplifiers 14 are transferred to the data latch circuits 16. Selected one of latched data of the data latch circuits 16 is passed through the column selection gate 19, which is selected when the column decoder 18 decodes the column address signal input, and outputted to an external data bus through the data bus (DQ, /DQ) and the I/O buffer 20. Further, a bit line equalizer 25 is provided between the sense amplifier 14 and the transfer gate 15, which set the sense amplifier 14 in a precharge state in accordance with an equalizing signal EQ.
In the above operation, the transfer gates 15 are turned off at the time when the data are transferred to the data latch circuits 16, whereby the DRAM cell array 10 and the sense amplifiers 14 can be independently operated from the operation of the data latch circuits 15 and the followings.
By use of the above operation, while transferring of data on the same row are performed between the data latch circuit 16 and the external data bus, a next row address signal is inputted, and new data on the same row corresponding to the new row address are read to the sense amplifier 14 from the cell array 10. Thereby, at the time when the transfer of latched data to the external data bus from the data latch circuit 16 is ended, the transfer gate 15 is turned on again, and new data can be transferred to the data latch circuit 16 from the sense amplifier 14.
In FIG. 3, for example, a data corresponding to the row address A is read out to a bit line pair (BL, /BL) and latched by the sense amplifier 14. When the transfer gate control signal is activated, the data is transferred to the data latch circuit 16 through the transfer gate 15, thus the state of the data line pair (DL, /DL) is renewed and held even after the transfer gate signal is inactivated. In synchronization with /CAS (column address strobe) signal, the data corresponding to the column address Q is read out to the data bus (DQ, /DQ). In the meantime, a data corresponding to the row address B is read out to the bit line pair (BL, /BL) and latched by the sense amplifier 14. When the following one of the transfer gate control signal is activated, the state of the data line (DQ, /DQ) is renewed again. In synchronization with the next one of the /CAS signal, the data corresponding to the column address R is read out to the data bus (DQ, /DQ).
Therefore, when the DRAM is viewed from the external bus side, there seemingly disappears the time (normally 50 ns or more) which is necessary to read out data corresponding to the row address input from the DRAM array 10 to the sense amplifier 14. In other words, after a short period of time (for example, within 10 ns), which is required to turn off the transfer gate 15 after the transfer gate 15 is turned on to transfer data to the data latch circuit 16 from the sense amplifier 14, new data can be read out again from the data latch circuit 16. In the example of FIG. 3, a new data is read out after 20 ns.
However, there were problems in the above-explained the conventional word line driving system of DRAM with data latch as follows.
As mentioned above, the word line WL is activated, data is read out to the sense amplifier 14 from the memory cell MC. Then, data is transferred to the data latch circuit 16, and synchronized with the rising edge of the /RAS signal, and the word line WL is inactivated. Sequentially, the sense amplifier activation signals /SAN and SAP are inactivated, and the voltages of the pair of the bit lines (BL, /BL), which are connected to the pair of input/output terminals of the sense amplifiers 14, are equalized by an equalizer 25, activated by an equalizing signal EQ which is synchronized with the pulse edges of the /RAS signal. In this case, if the word line WL is once activated, the word line is normally set to be in the activated state up to the rising edge of the /RAS signal for 60 ns or more.
Therefore, a ratio of the time in which the word line boosted voltage is applied to a gate insulating film of the MOS transistor Q for a transfer gate of the memory cell MC connected to the word line WL to the total operating time, that is, a duty ratio is increased. Due to this, it is difficult to ensure a long-time reliability of the gate insulating film. Moreover, there must be correspondingly increased test time for performing a screening test of the gate insulating film in a wafer state or after the packaging. Due to this, a test cost is increased.